The operating clock frequency is an important performance metric of a high performance VLSI integrated circuit product. Integrated circuits with higher operating speeds usually provide higher performance and demand higher profit on the market. Accordingly, when designing an integrated circuit product, an important part of the design process is trying to increase the useful clock frequency of the circuit through several design iterations (or design steppings). Typically, at each design iteration, debug engineers will try to increase the clock frequency of a design through a “speed-path” debug process. The purpose of the speed-path debug process is to identify the speed-limiting critical paths (sometimes referred to as “speed paths”) inside a circuit design, so that they can be corrected in the next design iteration.
A signal propagation path in a circuit starts with a primary input (for example, a flip-flop), ends at a primary output (for example, another flip-flop), and includes the intermediate circuit devices through which the signal passes during its travel from the primary input to the primary output. If the signal propagation delay along a path is longer than the specified clock period, an error will occur at the primary output (that is, the signal propagation will fail to accurately and timely transmit the signal). A critical signal propagation path is a path that carries a signal that must be accurately and timely delivered to its destination for the integrated circuit to operate as intended. Given a design with the specified clock frequency F, if the clock frequency of this design is increased to F—incr, then one or more critical signal propagation paths in the design might fail due to the relatively faster clock frequency.
Debug engineers have used functional test patterns to identify performance limiting critical paths in an integrated circuit design, usually with the assist of design-for-debug features. Functional pattern based speed path debug typically requires a great deal of design experience, architectural knowledge of a specific design and the knowledge of the functionality of a specific failing test pattern, however. Further, due to the long test sequences in a functional test pattern, a failure induced by a functional test pattern may take many cycles to reach an observable output. Thus, using functional pattern failures to identify a performance limiting signal propagation path can be a time-consuming task. While speed path debug for functional patterns can be automated, the automation usually depends on the design-for-debug circuit features embedded inside a design and in most cases is very design specific.
More recently, with the wide adoption of the scan design-for-test methodology, at-speed scan test patterns also have been used to diagnose timing related design errors or manufacturing defects. For example, at-speed scan test patterns have been used to identify delay defects during product silicon debug. Traditional logic fault diagnosis techniques are mainly based on the SLAT (Single Location At a Time) concept. The SLAT concept assumes a single defect for each failing pattern. Similar concepts have been applied to diagnose at-speed defects using path delay fault models or gate transition delay fault models. While the SLAT concept has been shown to be effective for diagnosing manufacturing defects, it may not be sufficient for speed path debug where multiple paths are exercised in a single test pattern. Another challenge to scan-based at-speed diagnosis is that, traditionally, this type of diagnosis tries to isolate the fewest suspect signals that can explain all of the failing bits. For speed path debug, however, the target of the diagnosis is to identify all of the failing signal propagation paths that cause failures during the application of at-speed scan test patterns.
Path delay fault models have been used to diagnose delay defects, but the diagnostic resolution for path delay faults has not achieved an acceptable level, especially when there are multiple faults in the circuit under diagnosis. To improve the diagnosis resolution of path delay faults, the use of additional test patterns has been proposed to target sensitized paths. The additional patterns can be used to find the delay bound of suspect paths to help improve diagnostic resolution. However, iteratively generating test patterns for each sensitized path and then applying the test patterns to derive the delay bounds might be a very time consuming process when the number of paths to be considered is large.
Static timing analysis (STA) and statistical timing analysis also have been employed to diagnose delay defects or identify speed paths based on at-speed scan test patterns. The speed paths are identified based on the path delay calculated for different test corners (i.e. temperature or voltage corners) by an STA tool. There are several problems with this type of STA analysis, however. First, STA is pattern independent. This usually causes the STA techniques to identify many paths that are not performance limiting as suspect speed paths. Second, due to the inaccuracy of the timing model, STA could miss actual critical speed paths.